Modern integrated circuit (IC) packages are constantly shrinking in size to accommodate their increasing use in handheld devices. Although the use of small IC packaging saves space in a host device, the connection points of a small IC package may require significant resources to properly connect to a substrate for integration into a system. Further, the same components used in handheld devices may also be used in larger systems and devices where space is not an issue. Using a small IC package in a larger system may result in unnecessary complexity and expense due to the difficulty of integration.
Processes have been developed for producing redistribution layers for repositioning the connection points of an IC package. These redistribution layers may bring the connection points of the IC package closer together (i.e., a “fan in” layer), or further apart (i.e., a “fan out” layer). Processes for developing redistribution layers often require specialized equipment, thereby driving up the cost of a system. Further, the produced redistribution layers may introduce undesirable parasitic capacitance or inductance into a system due to the thickness of the conductive material in the layer. Accordingly, a process is needed to produce a redistribution layer for the connection points of an IC package at a low cost while minimizing the impact of the layer on the operation of the IC device.